The bus system connects the various units in a computer system (memory, CPU, peripheral units) to one another and conveys the data interchange between them. The components of the electronic data processing system use a common transport path, the bus system(s), to which they are connected in parallel.
The coordination of the transmission, i.e. the selection of sender and receiver, the respective access and also the time synchronization are controlled by means of control signals. In the simplest case, bus control is performed by a sole bus master.
Basic execution of a data transfer on the respective bus system with a sole master which controls the access occurs essentially in three steps.
First, the master device provides an address for selecting a communication partner on the address bus in the bus system. The selected partner identifies this and goes into standby. By activating a control signal, for example for a read or write access operation, the master device determines the direction of transmission. The sender or slave device determined in this manner places the data onto the data bus. The master device performs the data transfer and signals that data transfer has concluded by deactivating the read or write signal. This returns the bus system to the initial state and means that it is ready for a subsequent transfer.
In “multimaster bus systems”, a plurality of master devices are authorized, in principle independently of one another, to use the bus system to address slave devices. To avoid collisions and disturbances during access via the bus system, a bus access rights controller needs to be provided in multimaster bus systems. A bus access rights controller normally uses a selection method (arbitration) to grant combinations of master devices and slave devices the respective access via the bus system.
Particularly in whole systems today which are integrated on a single semiconductor chip, “systems on a chip”, with multiple masters, it is desirable for the arbitration to be as flexible as possible. Only in this way is it possible to use the appropriate selection method which best matches a target application, for example an engine controller, an antilocking system, a signal processor in mobile radio applications etc.
On the basis of the prior art, two particular selection methods for bus access rights control are in use. On the basis of the priority selection method, all master devices are allocated a priority value. In the event of simultaneous access requests from various master devices, the arbitration controller or bus access rights controller always selects the requesting master device which has the highest priority for access to the bus system. Priority-controlled bus access allocation guarantees that urgent tasks, that is to say combinations of master and slave devices, are handled with priority. However, this may result in processes which have low priority never being executed. This is called starvation of a process.
On the basis of the second important access rights allocation method, the round robin method, all processes or bus access requests from master devices are executed in a fixed order. The round robin method therefore ensures that all active processes or requests from master devices to access slave devices via the bus system are assigned a guaranteed bus access time. In the case of the round robin method, however, all bus access operations, or requests to use the bus system for access, also have the same very long waiting time, which results from the maximum latencies of all the simultaneously active master devices. This means that bus system access which is more frequent or more important in a respective application is disadvantaged and the speed of the whole system on the semiconductor chip with an on-chip bus system and multiple masters is slowed.
Stipulating a single arbitration method or method for allocating bus access rights in multimaster bus systems has the fundamental drawback that the arbitration chosen in this manner cannot be optimum for all applications or target applications for the respective system on a chip.